1. Field of Invention
The present invention relates to a type of data transmission line. More particularly, the present invention relates to a type of data transmission line for connecting a microprocessor and a chipset.
2. Description of Related Art
In general, a microprocessor or a central processing unit (CPU) inside a personal computer is able to communicate with peripheral devices via a chipset. The chipset is an intermediate element for the exchange of data and control signals. The chipset has input/output leads that couple with a data transmission bus, and the bus leads to a connector above a main circuit board. Hence, any microprocessor plugged into the connector is able to communicate with the chipset directly.
Currently, the two most important bus specifications include gunning transceiver logic (GTL+) and high-speed transceiver logic (HSTL). GTL+bus is a standard specification created by Intel for transmitting data between a new generation of their microprocessors and external interfaces. The GTL+bus is suitable for high-speed microprocessors such as the Pentium II, Pentium III, the Pentium Pro and Socket 370. On the other hand, HSTL bus is an alternative specification employed by some microprocessors. The GTL+bus and the HSTL bus are really two different types of specifications. Hence, one chipset has to be used to interface with a microprocessor that employs a GTL+bus while another chipset has to be used to interface with a microprocessor that employs a HSTL bus.
FIG. 1 is a schematic diagram showing a GTL+data bus linking a microprocessor with a chipset. FIG. 2 is a schematic diagram showing a HSTL bus linking another microprocessor with a chipset. A few similarities between the transmission buses shown in FIGS. 1 and 2 can be found. Terminal voltages VTT for both of them are identical, for example, VTT=1.5V. Reference voltages VREF for both of them are also identical at about 1.0V (if VTT=1.5V), or VREF=⅔*VTT or 0.68* VTT. Both the GTL+bus 12 and the HSTL bus 22 use the same type of connectors 14 and 24 having identical dimensions. A microprocessor 16 having its own printed circuit board 16a is shown in FIG. 1. The circuit board 16a is plugged into a connector 14 above a main circuit board 10a so that the microprocessor 16 is connected to a chipset 10. Similarly, a microprocessor 26 having its own printed circuit board 26a is shown in FIG. 2. The circuit board 26a is plugged into a connector 24 above a main board 20a so that the microprocessor 26 is connected to a chipset 20.
A comparison of the GTL+bus and the HSTL bus shows that their differences lie mainly in the arrangement of the transmission lines. The GTL+transmission line 12 in FIG. 1 has one or two 56 ohms pull-up resistors Rtt to increase the bus voltage level. Because the resistor Rtt also happens to be close to the end of the transmission line, the resistor serves also as an end-termination resistor capable of preventing signal ring back. On the other hand, the HSTL transmission line 22 in FIG. 2 has two 100 ohms pull-up resistors Rtt to increase bus voltage level. The resistors Rtt do not serve as an end-termination resistor. The HSTL transmission line 22 further includes a serial resistor Rtt of about 22 ohms between the chipset 20 and the input/output (IO) terminals of the microprocessor 26. The resistor Rs mainly serves as a damper for transmission signals.
The aforementioned description illustrates that GTL+bus and HSTL bus are configured to follow two specifications from two different types of microprocessors. As a result, different chipsets must be used. Since a chipset is usually fixed onto the main board by manufacturers, a user""s choice of microprocessor is limited.
The invention provides a chipset capable of supporting different transmission buses so that a user is free to choose the type of microprocessor.
The invention provides an input/output buffer capable of detecting the type of microprocessor plugged into the connector on a main circuit board. Once the type of microprocessor is known, an appropriate amount of resistance can be automatically attached to the input/output leads of a chipset for operating the transmission bus of that particular type of microprocessor.
The invention also provides an input/output buffer capable of adjusting the amount of resistance attached to the input/output leads of a chipset. Hence, the same chipset can be used for operating different types of microprocessors each having a different transmission bus specification.
The invention also provides an input/output buffer having special circuits capable of reducing undesirable ring back from a transmission logic bus and lowering power consumption.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an input/output buffer capable of supporting a multiple of transmission buses. The input/output buffer is connected to various terminals of a microprocessor connector by a plurality of transmission lines. The input/output buffer comprises a coordinating controller; a logic control circuit for receiving a microprocessor-type signal from a microprocessor; a first transistor and a second transistor, in which one terminal of each transistor is coupled to an input/output pad of the input/output buffer while another terminal is grounded and a control terminal of each transistor is coupled to the logic control circuit; a first resistor element having three terminals, in which one terminal is coupled to a terminal voltage source while another terminal is coupled to a terminal of the first transistor and a control terminal of the first resistor element is coupled to the coordinating controller; a second resistor element having three terminals, in which one terminal is coupled to a terminal voltage source while another terminal is coupled to a terminal of the second transistor, a control terminal of the second resistor element being able to receive a control signal so that electrical conductivity of the second resistor element can be set; and a buffer having three terminals, in which one terminal is coupled to the input/output pad, one terminal is coupled to a reference voltage and an output terminal is coupled to the coordinating controller. The buffer receives a signal from the input pad and compares the signal with the reference voltage to produce an output voltage. The output voltage is sent to the coordinating controller so that resistance of the first resistor element is adjusted accordingly.
When the detection signal from the microprocessor is at a first voltage level such as a logic state of xe2x80x981xe2x80x99, both the first transistor and the second resistor remain conductive. The transmission line is configured according to the HSTL bus specification, for example. However, if the detection signal from the microprocessor is at a second voltage level such as a logic state of xe2x80x980xe2x80x99, the first transistor, the second transistor and the first resistor all remain conductive. The transmission line is configured to the GTL+bus specification, for example.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.